1. Field of the Invention
The present invention is directed to a semiconductor device and a manufacturing method thereof, especially to a semiconductor device having a pn junction, and to a technique for further reducing variations in breakdown voltage and on-state resistance in a device such as a diode or a vertical MOSFET.
2. Background of the Invention
A conventional manufacturing method of the vertical MOSFET having a breakdown voltage of 60 V or less will be described with reference to figures. FIGS. 21 through 32 are longitudinal sectional views illustrating the conventional manufacturing process.
First, an n.sup.+ silicon substrate 10 having a high impurity concentration is prepared (FIG. 21). Then, an n layer 11 having a low impurity concentration is epitaxially grown from a first major surface 10S1 of the silicon substrate 10 to the inside thereof to a thickness D (FIG. 22). On a first major surface 11S1 of the n layer 11, a SiO.sub.2 film 18 is formed by thermal oxidation (FIG. 23). After an opening hole 19 is formed in the SiO.sub.2 film 18, a P-type impurity is ion-implanted into the n layer 11 by utilizing the opening hole 19 (FIG. 24). The implanted impurity is diffused (FIG. 25), and a P-type impurity region 12 is formed by removing the SiO.sub.2 film 18 (FIG. 26).
Further, a gate oxide film 13 is formed by thermal oxidation (FIG. 27), and a polycrystalline silicon layer 14 to be a gate electrode is formed on the surface of the gate oxide film 13 (FIG. 28). An n.sup.+ source impurity region 15 having a high impurity concentration is selectively formed from the surface of the P-type impurity region 12 to a predetermined depth (FIG. 29). Then, an interlayer insulation film 16 is selectively formed on the exposed faces of the polycrystalline silicon layer 14 and on a surface portion of the n.sup.+ layer 15 on the side of the gate oxide film 13, so as to coat the gate oxide film 13 and the polycrystalline silicon layer 14 (FIG. 30). Further, a source electrode 17 is formed on the surface of the interlayer insulation film 16 and on the exposed portion of the first major surface of the n layer 11 (FIG. 31), while a drain electrode 20 is formed on a second major surface 10S2 of the n.sup.+ silicon substrate 10 (FIG. 32).
Next, the operation of the vertical MOSFET of FIG. 32 will be described.
When a positive gate voltage is applied to the polycrystalline silicon layer 14 to be a gate electrode, electrons are induced inside the surface of the P-type impurity region 12 just below the gate oxide film 13. If the gate voltage is further increased, an n-type channel region is narrowly formed. If a positive voltage is applied to the drain electrode 20) at this time, the layers 11 and 15 become conductive, by which an electron current flows from the source electrode 17 to the drain electrode 20.
This electron current is related to the impurity concentration and thickness of the n layer 11. Since impurity concentration is expressed by resistivity, the electron current depends on the resistivity and thickness of the n layer 11. Thus, the on-state resistance generated by a rated electron current flowing through each of the layers 15, 12, 11, 10, depends on the resistivity and thickness of the n layer 11.
There is a depletion layer region at a pn junction of the semiconductor device, and the width of the depletion layer region is related to the impurity concentration and thickness both of the p-type and n-type regions. The breakdown voltage between the pn junction is also related to the impurity concentration and thickness of the p-type and n-type regions, because it depends on the electric field generated by the voltage applied to the depletion layer region. Especially for the vertical MOSFET of FIG. 32, since the depletion layer region basically extends to a region of low impurity concentration, the breakdown voltage between the source electrode 17 and the drain electrode 20 is closely related to the impurity concentration (or resistivity) and thickness of the n layer 11.
Since the conventional vertical MOSFET with a breakdown voltage of 60 V or less has such a structure as described above, variations in impurity concentration and thickness of the n layer on the drain side cause variations in characteristics such as on-state resistance or breakdown voltage dependent on the resistivity and thickness of the n layer. Further, in the conventional technique, the epitaxial growth of the n layer (FIG. 22) in element manufacture inevitably causes about .+-.10% variations in resistivity and thickness, which cannot be ignored. Besides, the thermal treatment in the element manufacture causes a float of a high concentration of impurity from the n-type silicon substrate, which substantially reduces the thickness D of FIG. 22 and thereby increases resistivity. Therefore, the relation of the thickness D of FIG. 22 and the thickness DIP of FIG. 32 can be expressed as D&gt;DIP. Here, the term "float" indicates that, in FIG. 32, for example, some of the n-type impurity in the n.sup.+ layer 10 is diffused in the n layer 11 so that the n.sup.+ layer 10 extends to the n layer 11. This increases the impurity concentration of the n layer 11 as indicated by the broken line BC of FIG. 20.
First, if the resistivity of the n layer varies upward in the epitaxial growth of the n layer and is further increased due to the float of a high concentration of impurity from the n-type silicon substrate, the on-state resistance becomes higher than the desired value. That is, the resistivity .rho. becomes .rho.+.alpha. due to the epitaxial growth, and further becomes .rho.+.alpha.+.beta. due to the float of a high concentration of impurity, reducing the thickness D of the n layer. At this time, since the increase in on-state resistance due to the increase in resistivity .rho. is greater than the reduction in on-state resistance due to the reduction in thickness D, the on-state resistance is increased. On the other hand, the breakdown voltage is not reduced.
Secondly, if the resistivity of the n layer varies downward in the epitaxial growth of the n layer, and further the thickness of the n layer is reduced due to the float of a high concentration of impurity from the n type silicon substrate, the breakdown voltage is reduced. In this case, the resistivity does not change, so that the reduction in thickness D comes to have a great effect. Thus, not the increase in on-state resistance but the reduction in breakdown voltage introduces a problem.
The above-described problem that the variations in resistivity and thickness of the n layer causes the variations in characteristics such as on-state resistance and breakdown voltage, is especially significant for the vertical MOSFET having a breakdown voltage of 60 V or less, but may also arise for the vertical MOSFET having a breakdown voltage of more than 60 V, and for a pin-structured diode to be used as a free wheeling diode in a power module.